OpenSSL: enable asm optimisations on RISC OS

2 files changed, 139 insertions, 1 deletions

diff --git a/sdk/recipes/patches/openssl/Configure.p b/sdk/recipes/patches/openssl/Configure.p
index 9d4ba20..96062db 100644
--- a/sdk/recipes/patches/openssl/Configure.p
+++ b/sdk/recipes/patches/openssl/Configure.p
@@ -4,7 +4,7 @@
  "beos-x86-r5",   "gcc:-DL_ENDIAN -DTERMIOS -O3 -fomit-frame-pointer -mcpu=pentium -Wall::-D_REENTRANT:BEOS:-lbe -lnet:BN_LLONG ${x86_gcc_des} ${x86_gcc_opts}:${x86_elf_asm}:beos:beos-shared:-fPIC -DPIC:-shared:.so",
  "beos-x86-bone", "gcc:-DL_ENDIAN -DTERMIOS -O3 -fomit-frame-pointer -mcpu=pentium -Wall::-D_REENTRANT:BEOS:-lbe -lbind -lsocket:BN_LLONG ${x86_gcc_des} ${x86_gcc_opts}:${x86_elf_asm}:beos:beos-shared:-fPIC:-shared:.so",
  
-+"arm-unknown-riscos","arm-unknown-riscos-gcc:-DL_ENDIAN -DTERMIOS -DNO_SYS_UN_H -O3 -fomit-frame-pointer -Wall::-D_REENTRANT:::BN_LLONG DES_RISC1::::::::::::::::::::echo",
++"arm-unknown-riscos","arm-unknown-riscos-gcc:-DL_ENDIAN -DTERMIOS -DNO_SYS_UN_H -O3 -fomit-frame-pointer -Wall::-D_REENTRANT:::BN_LLONG RC4_CHAR RC4_CHUNK DES_INT DES_UNROLL BF_PTR:${armv4_asm}:::::echo",
 +"m68k-atari-mint","m68k-atari-mint-gcc:-DB_ENDIAN -DTERMIOS -DNO_SYSLOG -DNO_SYS_UN_H -DOPENSSL_USE_IPV6=0 -O3 -fomit-frame-pointer -Wall::-D_REENTRANT:::BN_LLONG DES_RISC1::::::::::::::::::::m68k-atari-mint-ranlib",
 +"m5475-atari-mint","m5475-atari-mint-gcc:-DB_ENDIAN -DTERMIOS -DNO_SYSLOG -DNO_SYS_UN_H -DOPENSSL_USE_IPV6=0 -O3 -fomit-frame-pointer -Wall::-D_REENTRANT:::BN_LLONG DES_RISC1::::::::::::::::::::m5475-atari-mint-ranlib",
 +"m68k-unknown-amigaos","m68k-unknown-amigaos-gcc:-DB_ENDIAN -DOPENSSL_SYS_AMIGAOS3 -DNO_SYSLOG -DHAVE_FORK=0 -DNO_SYS_PARAM_H -DNO_SYS_UN_H -O3 -fomit-frame-pointer -Wall::-D_REENTRANT::-lnet -lm:BN_LLONG DES_RISC1::::::::::::::::::::m68k-unknown-amigaos-ranlib",
diff --git a/sdk/recipes/patches/openssl/arm-unknown-riscos/armv3.p b/sdk/recipes/patches/openssl/arm-unknown-riscos/armv3.p
new file mode 100644
index 0000000..7f4d3bf
--- /dev/null
+++ b/sdk/recipes/patches/openssl/arm-unknown-riscos/armv3.p
@@ -0,0 +1,138 @@
+--- crypto/arm_arch.h	2015-07-09 12:21:24.000000000 +0000
++++ crypto/arm_arch.h	2015-11-13 13:47:02.386910047 +0000
+@@ -31,6 +31,8 @@
+ #    define __ARM_ARCH__ 5
+ #   elif defined(__ARM_ARCH_4__) || defined(__ARM_ARCH_4T__)
+ #    define __ARM_ARCH__ 4
++#   elif defined(__ARM_ARCH_3__)
++#    define __ARM_ARCH__ 3
+ #   else
+ #    error "unsupported ARM architecture"
+ #   endif
+--- crypto/armcap.c	2015-07-09 12:21:24.000000000 +0000
++++ crypto/armcap.c	2015-11-13 15:12:20.385640267 +0000
+@@ -7,6 +7,8 @@
+ 
+ #include "arm_arch.h"
+ 
++extern unsigned int __get_cpu_arch (void);
++
+ unsigned int OPENSSL_armcap_P;
+ 
+ static sigset_t all_masked;
+@@ -67,13 +69,15 @@
+     sigprocmask(SIG_SETMASK, &ill_act.sa_mask, &oset);
+     sigaction(SIGILL, &ill_act, &ill_oact);
+ 
+-    if (sigsetjmp(ill_jmp, 1) == 0) {
+-        _armv7_neon_probe();
+-        OPENSSL_armcap_P |= ARMV7_NEON;
+-    }
+-    if (sigsetjmp(ill_jmp, 1) == 0) {
+-        _armv7_tick();
+-        OPENSSL_armcap_P |= ARMV7_TICK;
++    if (__get_cpu_arch() == 0) {
++        if (sigsetjmp(ill_jmp, 1) == 0) {
++            _armv7_neon_probe();
++            OPENSSL_armcap_P |= ARMV7_NEON;
++        }
++        if (sigsetjmp(ill_jmp, 1) == 0) {
++            _armv7_tick();
++            OPENSSL_armcap_P |= ARMV7_TICK;
++        }
+     }
+ 
+     sigaction(SIGILL, &ill_oact, NULL);
+--- crypto/modes/asm/ghash-armv4.pl	2015-07-09 12:21:24.000000000 +0000
++++ crypto/modes/asm/ghash-armv4.pl	2015-11-13 13:44:26.274913291 +0000
+@@ -157,7 +157,14 @@
+ 	ldmia	$Thh,{$Tll-$Thh}	@ load Htbl[nhi]
+ 	add	$nhi,$nhi,$nhi
+ 	eor	$Zll,$Tll,$Zll,lsr#4
++#if __ARM_ARCH__>=4
+ 	ldrh	$Tll,[sp,$nhi]		@ rem_4bit[rem]
++#else
++	add	$len,$nhi,#1
++	ldrb	$len,[sp,$len]
++	ldrb	$Tll,[sp,$nhi]
++	orr	$Tll,$Tll,$len,lsl#8
++#endif
+ 	eor	$Zll,$Zll,$Zlh,lsl#28
+ 	ldrb	$nhi,[$Xi,#14]
+ 	eor	$Zlh,$Tlh,$Zlh,lsr#4
+@@ -180,7 +187,14 @@
+ 	eor	$Zll,$Zll,$Zlh,lsl#28
+ 	eor	$Zlh,$Tlh,$Zlh,lsr#4
+ 	eor	$Zlh,$Zlh,$Zhl,lsl#28
++#if __ARM_ARCH__>=4
+ 	ldrh	$Tll,[sp,$nlo]		@ rem_4bit[rem]
++#else
++	add	$len,$nlo,#1
++	ldrb	$len,[sp,$len]
++	ldrb	$Tll,[sp,$nlo]
++	orr	$Tll,$Tll,$len,lsl#8
++#endif
+ 	eor	$Zhl,$Thl,$Zhl,lsr#4
+ 	ldrplb	$nlo,[$inp,$cnt]
+ 	eor	$Zhl,$Zhl,$Zhh,lsl#28
+@@ -195,7 +209,14 @@
+ 	ldrplb	$Tll,[$Xi,$cnt]
+ 	eor	$Zll,$Zll,$Zlh,lsl#28
+ 	eor	$Zlh,$Tlh,$Zlh,lsr#4
+-	ldrh	$Tlh,[sp,$nhi]
++#if __ARM_ARCH__>=4
++	ldrh	$Tll,[sp,$nhi]		@ rem_4bit[rem]
++#else
++	add	$len,$nhi,#1
++	ldrb	$len,[sp,$len]
++	ldrb	$Tll,[sp,$nhi]
++	orr	$Tll,$Tll,$len,lsl#8
++#endif
+ 	eor	$Zlh,$Zlh,$Zhl,lsl#28
+ 	eor	$Zhl,$Thl,$Zhl,lsr#4
+ 	eor	$Zhl,$Zhl,$Zhh,lsl#28
+@@ -245,7 +266,14 @@
+ 	ldmia	$Thh,{$Tll-$Thh}	@ load Htbl[nhi]
+ 	add	$nhi,$nhi,$nhi
+ 	eor	$Zll,$Tll,$Zll,lsr#4
++#if __ARM_ARCH__>=4
+ 	ldrh	$Tll,[$rem_4bit,$nhi]	@ rem_4bit[rem]
++#else
++	add	$inp,$nhi,#1
++	ldrb	$inp,[$rem_4bit,$inp]
++	ldrb	$Tll,[$rem_4bit,$nhi]
++	orr	$Tll,$Tll,$inp,lsl#8
++#endif
+ 	eor	$Zll,$Zll,$Zlh,lsl#28
+ 	eor	$Zlh,$Tlh,$Zlh,lsr#4
+ 	eor	$Zlh,$Zlh,$Zhl,lsl#28
+@@ -266,7 +294,14 @@
+ 	eor	$Zll,$Zll,$Zlh,lsl#28
+ 	eor	$Zlh,$Tlh,$Zlh,lsr#4
+ 	eor	$Zlh,$Zlh,$Zhl,lsl#28
++#if __ARM_ARCH__>=4
+ 	ldrh	$Tll,[$rem_4bit,$nlo]	@ rem_4bit[rem]
++#else
++	add	$inp,$nlo,#1
++	ldrb	$inp,[$rem_4bit,$inp]
++	ldrb	$Tll,[$rem_4bit,$nlo]
++	orr	$Tll,$Tll,$inp,lsl#8
++#endif
+ 	eor	$Zhl,$Thl,$Zhl,lsr#4
+ 	ldrplb	$nlo,[$Xi,$cnt]
+ 	eor	$Zhl,$Zhl,$Zhh,lsl#28
+@@ -280,7 +315,14 @@
+ 	eor	$Zll,$Tll,$Zll,lsr#4
+ 	eor	$Zll,$Zll,$Zlh,lsl#28
+ 	eor	$Zlh,$Tlh,$Zlh,lsr#4
++#if __ARM_ARCH__>=4
+ 	ldrh	$Tll,[$rem_4bit,$nhi]	@ rem_4bit[rem]
++#else
++	add	$inp,$nhi,#1
++	ldrb	$inp,[$rem_4bit,$inp]
++	ldrb	$Tll,[$rem_4bit,$nhi]
++	orr	$Tll,$Tll,$inp,lsl#8
++#endif
+ 	eor	$Zlh,$Zlh,$Zhl,lsl#28
+ 	eor	$Zhl,$Thl,$Zhl,lsr#4
+ 	eor	$Zhl,$Zhl,$Zhh,lsl#28