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| author | John-Mark Bell <jmb@netsurf-browser.org> | 2022-06-01 10:28:20 +0100 |
|---|---|---|
| committer | John-Mark Bell <jmb@netsurf-browser.org> | 2022-11-01 20:24:06 +0000 |
| commit | 2021fafbbafbaa7f8a53ac290b431179c6ec038f (patch) | |
| tree | 0cbe10e631b4b8f9989d61c0221f35c015fc3c71 | |
| parent | 1adf75a71b1a8dde55047f8da8a7ba4e1436d257 (diff) | |
| download | toolchains-2021fafbbafbaa7f8a53ac290b431179c6ec038f.tar.gz toolchains-2021fafbbafbaa7f8a53ac290b431179c6ec038f.tar.bz2 | |
Disable halfword accesses by default.
We don't want these at all until such time as we drop support for
the Risc PC. Due to the unique way that its bus operates (it was
designed for armv3 parts), 16bit accesses fail horribly, even if
the CPU supports armv4 (like StrongARM does). Disabling this by
default ensures that everything built by this toolchain should
run happily on such systems (unless someone explicitly opts in to
LDRH/STRH generation by passing -mhalfword-accesses). Note that
other armv4 access instructions (such as LDRSB) are not affected
by this option at all.
| -rw-r--r-- | arm-riscos-gnueabihf/recipes/patches/gccsdk/gcc-default-no-halfword-access.p | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arm-riscos-gnueabihf/recipes/patches/gccsdk/gcc-default-no-halfword-access.p b/arm-riscos-gnueabihf/recipes/patches/gccsdk/gcc-default-no-halfword-access.p new file mode 100644 index 0000000..400341f --- /dev/null +++ b/arm-riscos-gnueabihf/recipes/patches/gccsdk/gcc-default-no-halfword-access.p @@ -0,0 +1,13 @@ +Index: gcc/gcc.config.arm.arm.opt.p +=================================================================== +--- gcc/gcc.config.arm.arm.opt.p (nonexistent) ++++ gcc/gcc.config.arm.arm.opt.p (working copy) +@@ -5,7 +5,7 @@ + that may trigger Cortex-M3 errata. + + +mhalfword-access +-+Target Report Var(halfword_access) Init(1) +++Target Report Var(halfword_access) Init(0) + +Enable halfword memory accesses. + + + munaligned-access |